The present invention relates to semiconductor devices and methods for fabricating the devices, and particularly relates to semiconductor devices including fully-silicided (FUSI) gate electrodes and methods for fabricating the devices.
In the field of semiconductor devices, increase of speed and reduction of power consumption are accelerated because of rapid miniaturization of elements in recent years. Accordingly, enhancement of transistor performance is urgently needed. However, conventional miniaturization of elements alone is now insufficient for enhancement of transistor performance.
In view of this, in a metal insulator semiconductor (MIS) transistor, a film having a high dielectric constant (i.e., a high-κ film) is used as a gate insulating film and a gate electrode is fully made of a metal so that reduction of gate leakage current and enhancement of transistor driving ability are both achieved.
FIGS. 16A and 16B illustrate a full silicidation process in a method for fabricating a conventional MIS transistor. FIG. 16A is a cross-sectional view in the gate width direction and FIG. 16B is a cross-sectional view in the gate length direction (see, for example, International Electron Device Meeting p. 95, 2004). As illustrated in FIGS. 16A and 16B, first, an isolation region 102 is selectively formed in a semiconductor substrate 101, thereby forming an active region 101a. Then, a gate insulating film 103 and a gate electrode film 104 made of polysilicon are deposited. Thereafter, the gate electrode film 104 is patterned such that the ends of the gate electrode film 104 in the gate width direction are located inside the isolation region 102 when viewed from above. Subsequently, an offset sidewall 105 is formed on the side of the gate electrode film 104. Using the offset sidewall 105 and the gate electrode film 104 as a mask, an extension region 106 and a pocket region 107 having a conductivity different from that of the extension region 106 are sequentially formed below the side of the offset sidewall 105 in the active region 101a. Thereafter, a sidewall 108 is formed at the side of the gate electrode film 104 with the offset sidewall 105 interposed therebetween. Using the sidewall 108, the offset sidewall 105 and the gate electrode film 104 as a mask, a source/drain region 109 is formed below the side of the sidewall 108 in the active region 101a. Then, only an upper portion of the source/drain region 109 is selectively silicided, thereby forming a silicide layer 110. Subsequently, an interlayer insulating film 111 is formed on the semiconductor substrate 101 and then is planarized by chemical mechanical polishing (CMP) until the gate electrode film 104 is exposed. Thereafter, an upper portion of the gate electrode film 104 is selectively removed by etching. Then, a nickel film 112 is deposited by sputtering over the interlayer insulating film 111 and the gate electrode film 104 having a reduced thickness. Subsequently, the nickel film 112 is subjected to heat treatment so that reaction occurs between polysilicon forming the gate electrode film 104 and nickel, thereby forming a gate electrode (FUSI gate electrode) in which the entire gate electrode film 104 is silicided.
However, in the method for fabricating a conventional semiconductor device, full silicidation, i.e., silicidation of the entire gate electrode, causes a problem in which the capacitance of the gate electrode increases.